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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch
September 2001 Revised December 2001
FIN1022 2 X 2 LVDS High Speed Crosspoint Switch
General Description
This non-blocking 2x2 crosspoint switch has a fully differential input to output data path for low noise generation and low pulse width distortion. The device can be used as a high speed crosspoint switch, 2:1 multiplexer, 1:2 demultiplexer or 1:2 signal splitter. The inputs can directly interface with LVDS and LVPECL levels.
Features
s Low jitter, 800 Mbps full differential data path s Worst case jitter of 190ps with PRBS = 223 - 1 data pattern at 800 Mbps s Rail-to-rail common mode range is 0.5V to 3.25V s Worst case power dissipation is less than 126 mW s Open-circuit fail safe protection s Fast switch time of 1.1 ns typical s 35 ps typical pin channel to channel skew s 3.3V power supply operation s Non-blocking switch s LVDS receiver inputs accept LVPECL signals directly s 7.5 kV HBM ESD protection s 16-lead SOIC package and TSSOP package s Inter-operates with TIA/EIA 644-1995 specification s See the Fairchild Interface Solutions web page for cross reference information: www.fairchildsemi.com/products/interface/lvds.html
Ordering Code:
Order Number FIN1022M FIN1022MTC Package Number M16A MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500653
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FIN1022
Connection Diagram
Pin Descriptions
Pin Name RIN0+, RIN1+ RIN0-, RIN1- Description LVDS non-inverting data inputs LVDS inverting data inputs
DOUT0+, DOUT1+ LVDS non-inverting data outputs DOUT0-, DOUT1- LVDS inverting data outputs EN0 EN1 SEL0 SEL1 VCC GND LVTTL input for enabling DOUT0+/DOUT0- LVTTL input for enabling DOUT1+/DOUT1- LVTTL input for selecting RIN0+/RIN0- or RIN1+/RIN1- for output DOUT0+/DOUT0- LVTTL input for selecting RIN0+/RIN0- or RIN1+/RIN1- for output DOUT1+/DOUT1- Power Supply Ground
Function Table
Inputs SEL0 L/O L/O H H X X L/O H X
O = OPEN
Outputs EN1 H H H H H H L/O L/O L/O DOUT0+ RIN0+ RIN0+ RIN1+ RIN1+ Z Z RIN0+ RIN1+ Z DOUT0- RIN0- RIN0- RIN1- RIN1- Z Z RIN0- RIN1- Z DOUT1+ RIN0+ RIN1+ RIN0+ RIN1+ RIN0+ RIN1+ Z Z Z
L = LOW Logic Level
SEL1 L/O H L/O H L/O H X X X
EN0 H H H H L/O L/O H H L/O
DOUT1- RIN0- RIN1- RIN0- RIN1- RIN0- RIN1- Z Z Z 1:2 Splitter Repeater Switch 1:2 Splitter
Mode
DOUT0 Disabled DOUT0 Disabled DOUT1 Disabled DOUT1 Disabled DOUT0 and DOUT1 Disabled
X = Don't Care Z = High Impedance
L / O = LOW or OPEN
H = HIGH Logic Level
Function Diagrams
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FIN1022
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Driver Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) 260C
-0.3V to +4.6V -0.3V to +4.6V -0.3V to +4.6V
Continuous
Recommended Operating Conditions
Supply Voltage (VCC) Input Voltage (VIN) Operating Temperature (TA) Electrostatic Discharge (HBM 1.5 k, 100 pF) Electrostatic Discharge (MM 0, 100 pF) 3.0V to 3.6V 0 to VCC
-40C to +85C >7500V >300V
-65C to +150C
150C
Note 1: The "Absolute Maximum Ratings": are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified (Note 2)
Symbol Parameter Test Conditions Min Typ (Note 3) 270 285 365 365 475 440 35 1.0 1.2 1.45 35 10 20 -10 -10 100 -100 0.05 VIN = GND VIN = V CC LVTTL Control Characteristics VIH VIL IIN VIK IPU/PD CIN COUT ICC Input High Voltage Input Low Voltage Input Current Input Clamp Voltage Output Power-Up/Power-Down High Z Leakage Current Input Capacitance Output Capacitance Power Supply Current No Load, All Drivers Enabled RL = 75 , All Drivers Enabled RL = 75 , All Drivers Enabled
Note 2: This part will only function with datasheet specification when a resistive load is applied to the driver outputs. Note 3: All typical values are at TA = 25C and with VCC = 3.3V.
Max
Units
LVDS Differential Driver Characteristics VOD Output Differential Voltage RL = 75 , See Figure 3 RL = 75 , See Figure 3 TA = 25C and VCC = 3.3V VOD VOS VOS IOZD IOFF IOS VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage Offset Magnitude Change from Differential LOW-to-HIGH Disabled Output Leakage Current Power-Off Current Short Circuit Output Current RL = 75 , See Figure 3 See Figure 3 See Figure 3 VOUT = 3.6V or GND, Driver Disabled VCC = 0V, VIN or VOUT = 3.6V or 0V VOUT = 0V, Driver Enabled VOUTx+ = 0V, VOUTx- = 0V, Driver Enabled LVDS Differential Receiver Characteristics VTH VTL VIC IIND Differential Input Threshold HIGH Differential Input Threshold LOW Input Common Mode Voltage Input Current (Differential Inputs) VIC = 0.05V or 1.2V or 3.25V VCC = 3.3V mV V A mV
mV V mV A A mA
3.25 20 20
2 0.8 VIN = 3.6V or GND IIK = -18 mA VCC = 0V to 1.5V 4.5 4.5 35 35 35 -1.5 10 20
V V A V A pF pF mA mA mA
Device Characteristics
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FIN1022
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol tPLHD tPHLD tTLHD tTHLD tPLH tPHL tZHD tZLD tHZD tLZD tSET tHOLD tJIT fTOG tSKEW Parameter Differential Output Propagation Delay LOW-to-HIGH Differential Output Propagation Delay HIGH-to-LOW Differential Output Rise Time (20% to 80%) Differential Output Fall Time (80% to 20%) Selection Propagation Delay LOW-to-HIGH (SELn to OUTn) Selection Propagation Delay HIGH-to-LOW (SELn to OUTn) Differential Output Enable Time from Z-to-HIGH Differential Output Enable Time from Z-to-LOW Differential Output Disable Time from HIGH-to-Z Differential Output Disable Time from LOW-to-Z Input (INn+/INn-) Setup Time to SELn Input (INn+/INn-) Hold Time to SELn Output Peak-to-Peak Jitter Maximum Toggle Frequency Within Device Channel-to-Channel Skew Pulse Skew |tPLHD -tPHLD| Part-to-Part Skew (Note 5)
Note 4: All typical values are at TA = 25C and with VCC = 3.3V. Note 5: Part-to-part skew is the maximum delay time difference on like edges (LOW-to-HIGH or HIGH-to-LOW) for the same VCC and temperature conditions.
Test Conditions
Min 0.7
Typ (Note 4)
Max 1.6
Units ns ns ps ps ns ns ns ns ns ns ns ns
RL = 75 , CL = 5 pF, VCC = 3.3V, TA = 25C See Figure 4 and Figure 5
1.0 0.7 1.0 290 290 0.6
1.2 1.2
1.3 1.6 1.3 580 580 1.5
RL = 75 , CL = 5 pF, VCC = 3.3V, TA = 25C See Figure 6 and Figure 7
0.9 0.6 0.9
1.1 1.1
1.2 1.5 1.2 3.5 3.5 3.5 3.5
RL = 75, CL = 5 pF See Figure 8 and Figure 9
See Figure 10 See Figure 10 223 -1 PRBS Sequence at 800 Mbps 50% Duty Cycle at 800 Mbps RL = 75 , CL = 5 pF, See Figure 4
0.5 0.5
0.3 0.3 190 20 35 80 225 500
ps ps Mbps ps ps ps
800
900 35 0 100
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FIN1022
Required Specifications
1. When the true and complement LVDS outputs (having a 75 connected between outputs) are connected to 3.75 k resistors and the common point of those 3.75 k resistors are connected to a voltage source that sweeps from 0 to 2.4V, the DC VOD and VOD are still maintained (see Figure 1). 2. When the true and complement LVDS outputs (having a 5 pF capacitor attached between outputs) are connected with 37.5 resistors each to common point, then the common point does not vary by more than 150 mV under all process, temperature and voltage conditions when the outputs switch either from LOW-toHIGH or from HIGH-to-LOW (see Figure 2). 3. Pull-down resistors are required on Enable (EN0 and EN1) and select (SEL0 and SEL1) inputs. 4. Fail safe protection on the outputs that draw less than 20 A of current (worst case) on the LVDS inputs. In this condition, if the input is in fail safe selected to OUT0+/OUT0- (say) and the outputs are Enabled then OUT0+ = HIGH and OUT0- = LOW. This prevents noise from being amplified when the connection is broken. 5. In the disabled state the outputs can go beyond VCC but there should be no appreciable leakage (see IOZD and IOFF specifications)
FIGURE 1. Common Mode Supply Test Circuit
FIGURE 2. Dynamic VOS Test Circuit and Waveforms
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FIN1022
Required Specifications
(Continued)
Note A: All input pulses have frequency = 50 MHz, tR or tF = 500 ps Note B: CL includes all probe and jig capacitances
FIGURE 3. LVDS Driver DC Test Circuit
FIGURE 4. LVDS Input to LVDS Driver Propagation Delay and Transition Time Circuit
FIGURE 5. LVDS Input to LVDS Output AC Waveforms
FIGURE 6. LVTTL Input to LVDS Driver Propagation Delay and Transition Time Test Circuit
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FIN1022
Required Specifications
(Continued)
Note A: All input pulses have frequency = 10MHz, tR or tF < = 1 ns. Note B: CL includes all probe and jig capacitances.
FIGURE 7. LVTTL Input to LVDS Output AC Waveforms
FIGURE 8. Differential Driver Enable and Disable Test Circuits
FIGURE 9. Enable and Disable AC Waveforms
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FIN1022
Required Specifications
(Continued)
FIGURE 10. Set-up and Hold Time Specification
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FIN1022
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A
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FIN1022 2 X 2 LVDS High Speed Crosspoint Switch
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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